About generation of do-not-generate fields

Say a parent struct is having two fields inside it. One is an ungenerated (with do-not-generate sign) child struct and another ungenerated field is of pre defined data types (like uint, bool etc.).

When this parent struct is generated

1) ungenerated field of pre defined data types will get their initial value (0 for scalars, NULL for structs, empty list for lists).

2) ungenerated field whose value is a range (such as [0..100]) gets the first value in the range.

3) ungenerated field of user defined data types (like sturcts) will not be allocated and none of the fields in it will be generated.

Take a look at following code.

<'

struct child_s

{

!a : uint (bits: 4);

b : uint (bits: 4);

};

struct top_s

{

!child : child_s;

!x : uint (bits: 3);

!y : uint (bits: 3);

keep x in [2..5];

};

extend sys

{

top : top_s;

};

'>

In this example, top_s struct has one ungenerated struct and two ungenerated fields of uint (bits: 3). When top is generated inside the sys

1) y will be generated and will get any random value between 0 and 7

2) x will be generated with value of 2 as it is a range bound ungenerated field.

3) child field will not be generated as it is defined as ungenerated struct. So, the fields a and b of child struct will not be generated as well.

By default MAIN sequence is not empty

By default, body method of MAIN sequence is not empty. It contains a loop which executes random number of times creating the sequence field (randomly unless constrained). The generated/created driver contains an instance of the MAIN sequence, which is started automatically upon run().

So, in your environment, if body method of MAIN sequence of any eVC is not made empty, it will start executing some random sequences at 0 simulation time. This might have adverse effect on the behavior of the stimulus given to the design if you are using virtual sequence, because user defined sequence (executed inside virutal sequence) and MAIN sequence might be running parallely and might be driving same signals and causing undesirable stimulus.

Debugging this will become difficult. You might be wondering why some other sequences are being executed even though you are calling perticular sequence only in virtual sequence?

So, if you are an eVC developer, always provide sequence library with body of MAIN sequence made empty. And if you are verifying any DUT and if you are using virtual sequence and not using MAIN sequence of any eVC, make body method of all MAIN sequences empty.

Take a look at this e code to check that how MAIN sequence is executing a loop which creates and executes the random sequence. Load this e code and give test command with random seed. You will see that even though body method of MAIN sequence is not extended, MAIN sequence is executing random sequneces (TEST1, TEST2, SIMPLE).