Specman Verification Questions - Part III

Question 1: What will be the output if following code is loaded and test command is issued into Specman ?

<'

struct x

{

y : uint;

keep soft y == 8;

};

extend sys

{

run() is also

{

var x : x;

gen x;

var a : uint = 2;

outf ("a = %d x.y = %d\n", a, x.y);

update_field(a);

update_struct(x);

outf ("a = %d x.y = %d\n", a, x.y);

};

update_field(a: uint) is

{

a = 4;

};

update_struct(x: x) is

{

x.y = 4;

};

};

'>

Answer:

a = 2 x.y = 8

a = 2 x.y = 4

Here, variable uint a is not updated and struct x is updated. Why is so? Because in specman, unlike user defined data types (e.g. structs, units), all variables with standard data types are passed by value in the methods. All user defined data types (like structs) are passed by reference. So, whenever, called methods update the passed structs, it is actually updating the original struct and not its copy.

If one wants user defined data types to be passed by value then he/she can use deep_copy to copy the existing variable and pass it to the method as shown below.

<'

struct x

{

y : uint;

keep soft y == 8;

};

extend sys

{

run() is also

{

var x : x;

gen x;

var a : uint = 2;

outf ("a = %d x.y = %d\n", a, x.y);

update_field(a);

update_struct(deep_copy(x));

outf ("a = %d x.y = %d\n", a, x.y);

};

update_field(a: uint) is

{

a = 4;

};

update_struct(x: x) is

{

x.y = 4;

};

};

'>

Question 2: What is the difference between inheritance implemented by "when" construct and implemented by "like" construct?

Answer:

like inheritance is the concept of the object oriented programming (OOP) where as when inheritance is the concept of aspect oriented programming (AOP). For more detail on AOP, please refer Aspect-Oriented Programming with the e Verification Language book written by David Robinson (Verilab).

like construct is used when someone wants to derive a child object from the already defined struct/unit. This derived child will have new struct/unit name. When someone derive the child object using when construct, the base name of the child will remain the same.

Another difference between like and when construct is that, once the child is derived using like inheritance, one can not add extra fields in the parent struct/unit, wherease, if child is derived using when construct, parent struct/unit can have extra fields.

Take a look at the following example. packet_valid field is added in the parent struct packet_s after the child is derived using like inheritance. This is not allowed and Specman will issue an error during loading phase.

<'

type packet_type_t : [GOOD, BAD, UGLY];

struct packet_s

{

kind : packet_type_t;

};

struct good_packet_s like packet_s

{

packet_size : uint (bits: 5);

};

extend packet_s

{

packet_valid : bool;

ack() is

{

outf ("NOTE :: This is packet %s\n", me);

};

};

extend sys

{

packet : packet_s;

good_packet : good_packet_s;

};

'>

Specman will issue following error.

*** Error: Cannot add new field 'packet_valid' to struct 'packet_s': it has like children (e.g. 'good_packet_s') with fields.

Note that ack() method will be added in the parent struct packet_s even though child is derived using like inheritance.

Specman Interview Questions - Part II

Follwing questions are taken from http://www.specman-verification.com/index.php?entry=entry061218-182034. Pleaser refer this page for all the answers.

1) What are the differences between structs and units?
2) What are the special unit related fields and methods?
3) How can you pass a struct by reference in e?
4) How do you pass basic types by reference?
5) What is the use of coverage per instance?
6) How can you use it to prevent the creation of fake coverage holes?
7) What logical structure (object structure) and physical structure (file structure) are defined by the eRM?
8) Which conventions are defined by the eRM?
9) What type of object is used as a container for an eVC?
10) What would you change in Specman?
11) What would you say are the main differences between work as an employee and as an independent consultant?
12) What do you normally do when you end a project?

Specman Interview Questions

Following questions are taken from http://www.specman-verification.com/static.php?page=WorkInterviewQuestions. Please refer this page for all the answers.

1) What are the differences between directed testbench and random testbench?
2) Draw the structure of a typical random testbench, describing each of the parts in detail.
3) Why is it important to keep code for generators/scoreboards and code for BFMs separated?
4) Is it a must to have an automatic checker (a scoreboard) in a directed testbench? Is it a must in a random testbench?
5) What is the difference between "protocol checking" and "data checking"? In which part of the testbench should each be done?
6) Which of the parts in the testbench should add data to the scoreboard?
7) What are the advantages and disadvantages of taking scoreboard data from the generator?
8) What are the advantages and disadvantages of taking scoreboard data from the BFM?
9) Suppose you have a scoreboard for a specific block inside the DUT. Will that scoreboard be useful during end to end (or full chip) tests as well? What for?
10) What is the use of the test file? Is it supposed to make the data that is generated by the testbench more or less random?
11) What is the difference between the constraints that are added through the test file, and those constraints that are placed in the environment files themselves?
12) Please explain the difference between declarative code (also known as static code), and sequential code, and give an example of each. What is the major advantage of controlling generation via declarative code? Which of the two is harder to debug?
13) What are test scenarios (also known as sequences)? What are they used for? Do the use of test scenarios makes the testbench more or less random?
14) Please give an example of when a test scenario should be used.
15) At which phase the use of sequences is more common at the beginning, at the middle, or at the end of the verification process?

Interview Questions

1) What will be the output when following code is loaded and "test" command is issued? (Easy)

<'
extend sys {
x : uint;
keep x < 45;
keep x in [0, 45, 190, 255];
run() is also { outf ("x = %d\n", x); };
};
'>

2) Write a temporal expression to verify that if event rdy_e has emitted then 3 clock cycles before, event req_e should have been triggered. The purpose of the check is to verify that rdy_e is not triggered without valid req_e. This should not be confused with "rdy_e should occur within 3 clock cycles of req_e". (Medium)

3) Write Sudoku solver in e. (Hard)

For more interview questions, please refer following links.

http://www.specman-verification.com/static.php?page=WorkInterviewQuestions http://digitalelectronics.blogspot.com/