Saturday, 20 August 2016

Tutorial on Portable Stimulus for SoC and System Verification/Validation

Portable Stimulus is one of the latest initiative by Accelerate to address stimulus reusability across the different axis like across different users (e.g. Architects, Design Engineer, Verification Engineer, Firmware development engineer), across different platforms (Simulation, Emulation, FPGA, Board) and across multiple integration level (IP, Subsystem, SoC, Firmware, OS). As the industry is adopting shift-left approach (i.e. bringing software development and testing early in the product cycle), portability of the stimulus id becoming more relevant and this is the need of an hour. If you are interested in knowing more about what's Cadence offerings in this exciting space, satay tuned for more as I am planning to write more on this in coming weeks.

DVCon India is here on 15-16 September, 2016 and I am going to talk about it in one of the tutorial "Using Portable Stimulus for SoC Verification as Applied on Mobile, Networking, and Server Designs". You can also explore Accellera tutorial "How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges" for more on portable stimulus.