Wednesday, 15 October 2008

Verification Engineer required for Cadence Design Systems, Bangalore or Noida

Experience: 4 to 5 years

Location: India, Bangalore or Noida

Job Requirement:
  • This engineer’s primary role will be to work in a team oriented environment to deliver digital logic design and verification methodologies, customised design environments and design implementation solutions that align with client goals. He/she will interact and work with other engineers on the worldwide D&V VCAD delivery team.
  • Responsibilities will include creating and customising design environments, design and verification methodologies.
  • Ideally the canddate should be able to assist with the optimisation of acceleration and emulation technologies using the Cadence Incisive verification flows including the Palladium and Xtreme hardware.
  • The engineer must have a solid background in logic design and verification experience with Cadence technology in the digital domain.
  • The client should have at least a basic understanding of modeling (e.g. Architecture or system), and both block and system level verification experiance, preferably with coverage driven methodologies.
  • The candidate should possess the necessary engineering and consultancy skills, i.e. that he/she is technically mature with the necessary communication skills to be able to consult effectively with clients, e.g. to talk to, coach and advise Customers.
  • The engineer must have a solid background in the electronics industry with at least 4 to 5 years experience, and should be willing to learn new technical and consulting skills.
Key Accountabilities:
  • Execution on VCAD Customer support projects, e.g. Implementation and functional verification of design systems.
  • Development of customer specific verification environments including components, methodology support, operation and maintenance.
  • Be prepared to provide design and verification support in VCAD Customer design projects, both remotely and onsite.
  • Ability to handle all design environment implementation tasks and architectural tasks with the minimum support or through working in a joint team of Cadence and Customer engineers.
  • Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.
  • Acquire a basic understanding of the (service) business environment of Cadence within 6 months including pre sales support.

Contact: getjobsinindia2007@gmail.com

DFT Engineer required for Cadence Design Systems, Bangalore

Experience: 3 to 6 Years

Location: Bangalore, India

Skill Sets: Scan, Jtag, Atpg, Tester interface.

Good to have skills: Exposure to ATPG tools like Encounter Test

Job Description:
  • This engineer’s primary role will be to work in a team oriented environment to deliver DFT activities for implementation services. He/she will interact and work with other engineers on the worldwide delivery team.
  • This engineer is expected to provide services using the following technical skills: Scan, JTAG, ATPG, Logic Synthesis, Static Timing Analysis, and to interface with designers / testing team.
  • In addition to the technical skills they will be expected to operate effectively in project teams delivering the design of leading edge. Additional responsibilities include customer interactions and pre-sales activities.
Key Accountabilities:
  • Ability to handle all design environment implementation tasks assigned, either personally or through supervising other Cadence and Customer engineers.
  • Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.
  • Acquire a basic understanding of the (service) business environment of Cadence including pre sales support.

Contact: getjobsinindia2007@gmail.com

OVM 2.0 Webinar on 16th Oct, 2008

There is a OVM 2.0 Webinar organized on 16th Oct, 2008.

Details of webinar is mentioned below.

Date : Thursday, October 16th, 2008
Time : 10:00 AM - 11:00 AM (Pacific Daylight Time)
Location : Online via Microsoft Office Live Meeting (details provided upon registration)

For more information and registration, please click here.

OVM 2.0 update contains some technical advances. Few of are listed bellow
  • Unified sequence mechanism
  • OVM User Guide
  • Improved debugging and expanded use of parametrized classes
  • Driver/sequencer communication enhancements