UVM-Multi Language solution from Cadence

Today's complex SoC level verification environment are based on advanced verification methodology standards. But these standards usually meant for single language domain. But fact of the life is that the these SoC level testbenches are made of mix of language domains like legacy Specman/e environment along with newly developed UVM-SV and SystemC or C++. Usually, when these scenario arrives, verification teams typically comes up with their own solutions which is mainly short term solution keeping existing needs in to the consideration. To develop this kind of inter operable solutions, there are quite a few challenges involved. Few are listed below.

1) Connecting different components of different domains
2) Transferring data/events from different domains
3) Synchronizations of major phases

Having said that, industry standard solution is the need of an hour. Cadence's Multi Language solution also known as UVM-ML addresses the above mentioned multi language integration challenges. UVM-ML is in existence for quite a sometime but least known. It was initially developed to take care of e-SV and e-SC integrations. UVM-ML is based on a back-plane library responsible for connecting two or more domains. Different language domain connect to back-plane library via language specific adapter layer. Currenty this solution supports integration of SystemC, UVM-SV, UVM-e.

Here is an example of how UVM-SV based producer can communicate to SystemC based consumer. You can refere more examples in the Incisiv installation area at $CDNS_HOME/tools/uvm/uvm_lib/uvm_ml/examples/sc/ and $CDNS_HOME/tools/uvm/uvm_lib/additions/uvm_ml_examples/ex_e_sv_sc_tlm/


//-----------------------------------------

//File : producer.sv
//System Verilog Producer
//-----------------------------------------

module topmodule;

import uvm_pkg::*;
`include "uvm_macros.svh"

//Declare basic packet which will be passed to SC consumer
class packet extends uvm_object;
   rand int data;
endclass

//Declare SV producer which will communicate with SC consumer through out port
class producer extends uvm_component;
   //Declare out port. This port will be connected to SC consumer
   uvm_analysis_port #(packet) out;

   //constructor
   function new(string name"producer", uvm_component parent=null);

      super.new(name, parent);
      out = new("out", this);

      //Register out port with UVM-ML
      ml_uvm::extnernal_if(out, "packet");

   endfunction : new

   //Generate dummy packet and pass it to out port
   task run_phase (uvm_phase phase);
      packet pkt = packet::type_id::create("pkt");

      phase.raise_objection(this);
      for (int i=0; i<5 br="" i="">      begin
         bit res = pkt.randomize();
         `uvm_info("TEST", $sformatf("producer.pkt.data='h%h", pkt.data), UVM_LOW)

         //Send the generated packet to out port
         out.write(pkt);
         #10;
      end

      phase.drop_objection(this);
   endtask : run_phase
endclass : producer

endmodule

//-----------------------------------------
//File : consumer.cpp

//SystemC Consumer

//-----------------------------------------
#include "ml_uvm.h";
#include "uvm.h";

using namespace tlm;
using namespace uvm;

class packet : public uvm_object
{
   UVM_OBJECT_UTILS(packet)
   public:
      int data;
};

UVM_OBJECT_REGISTER(packet)

//System C Consumer with templated with data type T
template <typename T>
class consumer : public uvm_compnent, public tlm_analysis_if
{
   public:
      sc_export > in;

   //constructor
   consumer(sc_module_name nm) : uvm_component(nm), in("in")
   {
      in(*this);
      //Register the export for mixed language communication
      ml_uvm::ml_uvm_register(&in);
   }

   UVM_COMPONENT_UTILS(consumer)

   //export implementation
   virtual void write( const T& t )
   {
      cout << sc_time_stamp() << " SystemC consumer receive a packet with data " << t.data << endl;
   }
};

UVM_COMPONENT_REGISTER_T(consumer, packet)

//System C testbench

SC_MODULE(TB)
{
   consumer c;
   SC_CTOR(TB) : c("consumer")
   {
      //Connect multi language port and export
      ml_uvm::ml_uvm_connect("producer.out", cons.in.name());
   }
};

Output Log:

UVM_INFO producer.sv(55) @ 0: producer [TEST] producer.pkt.data='h00000008
0 s SC consumer got a packet with data 8
UVM_INFO producer.sv(55) @ 10: producer [TEST] producer.pkt.data='h00000008
10 ns SC consumer got a packet with data 8
UVM_INFO producer.sv(55) @ 20: producer [TEST] producer.pkt.data='h00000003
20 ns SC consumer got a packet with data 3
UVM_INFO producer.sv(55) @ 30: producer [TEST] producer.pkt.data='h00000005
30 ns SC consumer got a packet with data 5
UVM_INFO producer.sv(55) @ 40: producer [TEST] producer.pkt.data='h00000006
40 ns SC consumer got a packet with data 6