Mixed HDL Hierarchy Code Generator

Sometime back, I wanted to experiment Specman environment with Mixed HDL (Verilog + VHDL) design. I wanted to have a simple 4 level hierarchical design with simple port connections. It took some time for me to build it as I need to refer VHDL and Verilog syntax. That time one thought came to my mind to have simple utility which can build this env very quickly so that I don't need to invest time to clean up the compilation errors.

Keeping this simple requirement in mind, I decided to build such a simple online tool which can be used by everybody.

I've created one Javascript based tool which can generate Mixed HDL Hierarchical design.Its link is http://www.sandipgor.com/hdl_ gen.html

I've tried to keep it simple. You can use "Add VHDL" and "Add Verilog" buttons to add VHDL or Verilog instance into hierarchy. "Level Up" and "Level Down" buttons can be used to increase/decrease current level where you want to add instances. Finally "Generate" button can be used to dump the hierarchical HDL code into the two text box placed right side of the window. I've also kept "Clear Code" and "Clear Hierarchy" buttons to clean up the relevent data. "Undo" button is useful to undo the last change. Remember, there is no "Redo" button though.

I hope you will find it useful. Please feel free to use it.

Any suggestion/feedback is welcome.