Ever came across the issue where one unit's signal map uses different signals from multi language design (VHDL and Verilog)? Take following example.
As shown in the diagram, top_wrapper is in vhdl and DUT is in verilog. Corresponding to this design, in e domain, two units are defined, one is top_wrapper_u and another dut_u.
Now, somewhere in dut_u unit, if you want to use clk from dut (verilog) and reset_n from top_wrapper (vhdl ), you can not do it using computed names (using strings). To achieve this, you have to use e external ports. Once ports are defined, using .agent() attribute of the units and ports, you can define, which unit/port is belonged to which design unit (vhdl/verilog).
As shown in the following code, refer the last line. reset_n.agent() is constrained to vhdl so that reset_n will be taken from vhdl module and rest of the ports in the dut_u will be taken from verilog module as dut_u.agent() is constrained to verilog.
<' unit dut_u
clk : in simple_port of bit is instance;
reset_n : in simple_port of bit is instance;
keep bind (clk, external);
keep bind (reset_n, external);
keep clk.hdl_path = "clk";
keep reset_n.hdl_path = "reset_n";
dut : dut_u is instance;
top : top_wrapper_u is instance;
keep top.hdl_path() == "~/top_wrapper";
keep top.dut.hdl_path() == "~/top_wrapper/dut";
keep top.agent() == "vhdl";
keep top.dut.agent() == "verilog";
keep top.dut.reset_n.agent() == "vhdl";